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Research Project: Agronomic and Engineering Solutions for Conventional and Organic Conservation Agricultural Systems in the Southeastern U.S.

Location: Soil Dynamics Research

Title: DME-8: A fully synthesizable 8-bit digital memristor emulator with FPGA-validated memristive dynamics

Author
item BORAH, S - University Of Texas At Tyler
item SEHURANI, P - University Of Texas At Tyler
item WALDECKER, P - University Of Texas At Tyler
item SUNDARAVADIVEL, P - University Of Texas At Tyler
item Torbert Iii, Henry

Submitted to: Meeting Abstract
Publication Type: Proceedings
Publication Acceptance Date: 4/10/2026
Publication Date: 7/22/2026
Citation: Borah, S.S., Sehurani, P.M., Waldecker, P., Sundaravadivel, P., Torbert III, H.A. 2026. DME-8: A fully synthesizable 8-bit digital memristor emulator with FPGA-validated memristive dynamics. Great Lakes Symposium on Very-large-scale integration.

Interpretive Summary: This paper presents Digital Memristor Emulator (DME-8), a synthesizable digital memristor emulator that translates continuous memristive dynamics into a finite-precision, clock-driven hardware architecture. Unlike physics-heavy analog models or device dependent emulators, the proposed framework reformulates voltage controlled memristive behavior into an 8-bit discrete-time state machine with threshold-controlled, polarity-dependent updates level SET/RESET programmability, and exact non-volatile retention under sub-threshold excitation.

Technical Abstract: This paper presents Digital Memristor Emulator (DME-8), a synthesizable digital memristor emulator that translates continuous memristive dynamics into a finite-precision, clock-driven hardware architecture. Unlike physics-heavy analog models or device dependent emulators, the proposed framework reformulates voltage controlled memristive behavior into an 8-bit discrete-time state machine with threshold-controlled, polarity-dependent updates level SET/RESET programmability, and exact non-volatile retention under sub-threshold excitation. Time-domain simulations demonstrate stable resistance modulation between programmable RON and ROFF limits with controlled quantization effects. The formulation is and bounded evolution. The emulator preserves canonical memristive fingerprints, including pinched hysteresis in the i-v plane, frequency-dependent hysteresis collapse, deterministic multi- implemented in ynthesizable Verilog, where the internal state is realized as an 8-bit register with comparator-based threshold detection and saturation logic. Behavioral verification in ModelSim confirms synchronous state transitions and precise retention, while Quartus Prime RTL synthesis shows direct mapping to standard digital primitives suitable for FPGA realization. By explicitly bridging memristive system theory with finite-state digital logic, DME-8 provides a deterministic, fabrication-free, and hardware-efficient abstraction of memristive behavior, enabling scalable integration into VLSI-based neuromorphic and in-memory computing architectures.